The present invention relates to a circuit arrangement wherein the output current of a phototransistor is used to control a thyristor and wherein a MOSFET, when placed in a conductive state, reduces the base current of the phototransistor whenever the thyristor voltage surpasses a prescribed value thereby inhibiting the triggering of the thyristor.
A circuit arrangement of the aforementioned type is known as a "zero point detector". Such a circuit arrangement is frequently employed in solid-state relays. European Patent Application EP-0 144 978 B1 describes a circuit arrangement for a solid-state relay. The zero point detector disclosed therein utilizes a MOSFET that is integrated between the base contact of a phototransistor and a terminal that is at a fixed voltage potential. The gate terminal of the MOSFET is connected, via a photodiode that is pulled in the inverse direction with respect to the thyristor voltage, with another terminal at which a voltage following the thyristor voltage lies. If the voltage following the thyristor voltage exceeds a prescribed value, and if the photodiode is exposed to light, the resulting increase in the inverse current charges the gate-source capacitance of the MOSFET and places it in a conductive state. As a result, the photocurrent of the phototransistor is reduced and the thyristor cannot be placed in its conductive state despite any exposure of the phototransistor to light.
The voltage window of the above-described circuit arrangement is not safely reproducible when the circuit is constructed in an integrated form. Therefore, it is an object of the present invention to set forth a circuit arrangement of the specified type having a voltage window that may be accurately reproduced even when the circuit is constructed as an integrated circuit. Within this voltage window, the connection/activation of the thyristor is possible. Outside of this voltage window, the connection/activation of the thyristor is prevented.